[Coco] Video sync issue... (crosspost)

[jdaggett at gate.net]

Okay 

Here is how the SYNC opcode works

The processor is placed in suspended operation and waits for an 
maskable or non maskable interrupt. If the F and I bits of the CC 
register is clear then the MPU will perform the corresponding IRQ 
service as set by one of the three vector addresses. 

IF the F and I bits of the CC register is set and the interrupt is and 
IRQ or FIRQ then the processor will not do the IRQ service interrupt 
and process the next instruction. 

The SYNC opcode will always wait and then process an NMI if and 
only if the NMI circuit is armed. The NMI ackknowledged circuit will 
not be armed until the first write to the S register establishing the 
stack after a hardware restart(RESET).

One other note if the Interrupt, maskable or non maskable, is less 
than 3 machine cycles then the Sync state is departed and 
processing continues as if nothing happened. T he key is that in 
order to sychronize to an external event the interrupt needs to be at 
least 3 machine cycles in duration. 

Yes this opcode is used to synchronize the processor instrructions 
to an external event through the interrupts. If  you do not want to 
execute ISR routine then the IRQ need be only one or two machine 
cycles long. 

The key here is that the NMI, FIRQ, and IRQ inputs are not edge 
level trtiggered. 

james


On 11 Nov 2004 at 22:27, Mark McDougall wrote:

Date sent:      	Thu, 11 Nov 2004 22:27:52 +1100
From:           	Mark McDougall 
<msmcdoug at optushome.com.au>
Organization:   	Technetium Development Pty Ltd
To:             	CoCoList for Color Computer Enthusiasts 
<coco at maltedmedia.com>
Subject:        	Re: [Coco] Video sync issue... (crosspost)
Send reply to:  	msmcdoug at optushome.com.au,
	CoCoList for Color Computer Enthusiasts 
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> Arthur Flexser wrote:
> 
> > The SYNC instruction suggests itself.....
> 
> No. This instruction will cause the processor to stop processing
> instructions and wait for an interrupt. It has nothing to do with
> video signals - nor could it as a CPU has no inherent knowledge of the
> surrounding hardware.
> 
> Regards,
> 
> -- 
> |              Mark McDougall                | "Electrical Engineers
> do it | <http://members.optushome.com.au/msmcdoug> |   with less
> resistance!"
> 
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