[Coco] assembly questions?

[Kevin Diggs]

Hi,

	I think they had to nuke U so they could use all the
addressing modes with the PC.

					kevin

jdaggett at gate.net wrote:
> 
> Mike
> 
> The Hitachi chip in Hitachi mode will shave two cycles off. In
> Motorola mode it is the same nu mber of cycles.
> 
> The 6809 is a state sequencer for instructions, unlike the 6309
> which actually uses  micrcoded instrtuctions. The 6809 can sort of
> be seen as each instruction being its own state machine. There are
> some unique adavatages that this has and one major disadvantage.
> The major disadvantage is real estate on the die. The major
> advantage is that some operations can be done asycronously and
> independent of the clock.
> 
> I started  investigating the possiblilty of how the 6809 could have
> been masked and I derived this so far. The Address Mode decode
> logic can be done without any clock by simply using or, and, and
> nand gates. A total of 38 logic gates. Looked at the opcode map
> and reduced the product terms to 38 logic gates. You can do the
> same for the post byte decode logic. I believe the post byte decode
> circuit is simpler.
> 
> Truly a neat processor. I told a manager of the HC11 line that the
> one thing that would have made the HC11 a better processor would
> have been to add the U register. The same holds for the HC12.
> 
> james
> On 23 Jul 2004 at 11:52, KnudsenMJ at aol.com wrote:
> 
> From:                   KnudsenMJ at aol.com
> Date sent:              Fri, 23 Jul 2004 11:52:45 EDT
> Subject:                Re: [Coco] assembly questions?
> To:                     coco at maltedmedia.com
> Send reply to:          CoCoList for Color Computer Enthusiasts
> <coco at maltedmedia.com>
>         <mailto:coco-
> request at maltedmedia.com?subject=unsubscribe>
>         <mailto:coco-
> request at maltedmedia.com?subject=subscribe>
> 
> > Thanks -- I myself have always wondered why TFR and EXG were so slow!
> > Part of the problem seem s to be always treating them as 16-bit
> > operations, so TFR A,B takes as long as TFR X,Y.
> >
> > And the other is using that internal temp reg, which turns out not to
> > be needed -- see below.
> >
> > In a message dated 7/23/04 7:53:52 AM Eastern Daylight Time,
> > jdaggett at gate.net writes:
> >
> > > with the TFR instrtruction the third and fourth cycle write R1 to a
> > > temp register internally. On cycle 5 and 6 the temp register is
> > > written to R2.
> >
> > This sounds like an explanation I heard years ago, but below we see
> > the temp wasn't needed. . .
> >
> > >  With the EXG instruction the third and fourth cycle writes R1 to
> > >  the temp
> > > register.
> > >  On the fifth and six instruction the contents of R2 is written to
> > >  R1. On
> > the
> > > seventh  and eighth cycles the temp register is sritten to R2.
> >
> > Since R2 was written directly to R1, the TFR instruction could have
> > bypassed the intermediate register too.  But I guess this
> > implementation simplified the control sequencing.  Remember, the 6809
> > was, and remains, the most sophisticated 8/16-bit micro ever made --
> > or darn close to it.
> >
> > Thanks again for the details.  BTW, does the 6309 cut out any of these
> > intermediate steps?  Maybe use a 16-bit internal bus?!?  --Mike K.
> >
> >
> > --
> > Coco mailing list
> > Coco at maltedmedia.com
> > http://five.pairlist.net/mailman/listinfo/coco
> 
> --
> Coco mailing list
> Coco at maltedmedia.com
> http://five.pairlist.net/mailman/listinfo/coco