[Coco] Bit 5 of DSKREG

[Neil Morrison]

----- Original Message ----- 
From: "Richard Batt" <dickbatt at buffalo.com>


> Hi Tim:
>
> I have 3 disk controllers but no schematics for any of them.
> However, I found the schematic for the FD-501 in the "Tandy's
> Little Wonder" book. This schematic shows the interrupt from
> the 1773 being gated before it leaves the disk controller as
> the NMI* signal.
>
> The gating is being done by part of U5, a LS02 chip, used as
> an AND gate with inverted inputs. If both inputs are low it
> outputs a hi. This hi is inverted by a separate gate (U6)to
> give the active low output NMI. The AND gate gets one of its
> low inputs from the 1773's int out inverted by another gate
> (chip unidentified) to give the low input to the AND gate.
>
> The other AND input receives the same signal as the DDEN*
> input on the 1773. This is the double density signal to
> the 1773, and is active low for dd. When this signal is low
> to the AND gate it allows the interrupt from the 1773 to pass
> thru to the NMI* output. So the disk controller will only
> output an NMI* when the disk controller is in dd mode.
>
> It seems a bit odd to me that the NMI* output would be linked
> to dd operation, but assuming the schematic is correct, that
> is how it works.

Oh no, that's perfectly sane. On the Model I, timing was done by
using a loop. When DD was implemented it needed some VERY tricky
programming. Tandy used interrupts on all later models with DD
drives, but SD could still be done by running in a loop. I suspect
that's what they had in mind here.

Neil