[Coco] Interrupt Confusion

[jdaggett at gate.net]

Robert

According to the databook I have the Control register is addressed 
when RS0 and RS1 are both high. It furthter states that bits 6 and 7 
of the control register are read only bits and are cleared with a read 
or a RESET. Can you then explain how this equates to an $xx02 
address? At $xx02 is the either the Data Direction Register or the 
Peripheral register depending on the state of bit 2 if the Control 
Register which is acessed at $xx03?

james
 

On 11 Jan 2004 at 21:22, Robert Gault wrote:

Date sent:      	Sun, 11 Jan 2004 21:22:31 -0500
From:           	Robert Gault <robert.gault at worldnet.att.net>
To:             	CoCoList for Color Computer Enthusiasts 
<coco at maltedmedia.com>
Subject:        	Re: [Coco] Interrupt Confusion
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> jdaggett at gate.net wrote:
> > 
> > On 11 Jan 2004 at 19:04, Brad Grier wrote:
> > 
> > To:             	coco at maltedmedia.com
> > From:           	Brad Grier <bradgrier at cox.net>
> > Date sent:      	Sun, 11 Jan 2004 19:04:11 -0600
> > Subject:        	[Coco] Interrupt Confusion
> > Send reply to:  	CoCoList for Color Computer Enthusiasts 
> > <coco at maltedmedia.com>
> > 	<mailto:coco-
> > request at maltedmedia.com?subject=unsubscribe>
> > 	<mailto:coco-
> > request at maltedmedia.com?subject=subscribe>
> > 
> >>I'm having having a problem with two games in Mocha that appear to
> >>be interrupt related - just when I thought I had all that ironed
> >>out!
> >>
> >>Here's my understanding of how things should work with regard to the
> >>60ms IRQ. Please let me know if I'm wrong.
> >>
> >>bit 0 of 0xff03 must be set to 1 to enable the interrupt
> >>bit 4 of the CC (IRQ Interrupt mask) must be set to zero for the cpu
> >>to process the interrupt.
> >>
> >>When an interrupt occurs, bit 7 of 0xff03 is turned on - another
> >>interrupt cannot occur until a read of 0xff02 which clears bit 7 of
> >>0xff03.
> >>
> > 
> > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > 
> > A read of $FF03 clears bit 7 of the PIA chip not $FF02.
> > 
> > Reading the interrupt flag of the control register clears the bit
> > when transistion by CA1/CB1.
> > 
> 
> No, that is not correct. A read of $FF03 does not clear the IRQ flag.
> A read of $FF02 clears the flag at $FF03.
> 
> ><snip>
> > james
> > 
> > 
> > 
> >>First question: if the CC register's IRQ mask is on, does an
> >>interrupt still fire (even though it's not processed by the CPU)
> >>causing bit 7 of 0xff03 to be set? In other words, do 'unprocessed'
> >>interrupts continue to fire if the CC register's IRQ flag is on?
> >>
> > 
> > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > If the 6809 is processing another IRQ event and the PIA chip IRQ
> > lines generate an IRQ that IRQ should be pending until the current
> > IRQ ISR is finished. The PIA flaf is cleared by reading the control
> > register. 
> > 
> > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > 
> >>Here's what's going on - I revised the interrupt code in Mocha to
> >>work according to the rules as I understand them (I had known it
> >>wasn't right but most stuff still worked). As a result, the Cyrus
> >>Chess program stopped processing keystrokes. I found if I set bit 7
> >>of 0xff03 after an interrupt but ONLY when the CC IRQ mask was on,
> >>the program would work fine. Before that, I was setting bit 7 as
> >>soon as mocha fired the IRQ (regardless of the state of CC
> >>register). I thought that fixed everything until...
> >>
> >>"Temple Of ROM" now breaks. If I turn on bit 7 of 0xff03 everytime I
> >>fire an IRQ regardless of the CC register's IRQ mask, TOR will work
> >>but Cyrus breaks! In TOR, it appears the CC IRQ mask is always on
> >>meaning the 6809 isn't processing IRQs but the program is somehow
> >>dependent on bit 7 of 0xff03 being handled as if IRQs were firing.
> >>What's going on?
> >>
> >>I must be missing something because I can't seem to find a solution
> >>that accomodates both of these programs.
> >>
> >>Any help would be greatly appreciated!!!
> >>
> >>Brad
> >>
> >>
> >>
> >>-- 
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> > 
> > 
> > 
> > 
> 
> 
> 
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