[Coco] Re: Interrupt Confusion

[Torsten Dittel]

> First question: if the CC register's IRQ mask is on, does an interrupt
> still fire (even though it's not processed by the CPU) causing bit 7 of
> 0xff03 to be set? In other words, do 'unprocessed' interrupts continue
> to fire if the CC register's IRQ flag is on?

I guess the Bit 7 will be set, just the IRQ isn't handeled (means:
nothing is saved on the stack, and no PC will follow the interrupt
vector). But I don't know what happens if interrupts are enabled in the
CC before this Bit 7 is cleared by reading from $FF02.

I once wrote a graphics demo switching heavily the video modes while
writing the scanlines on the monitor. I had to trigger to the field sync
interrupt as fast as possible (no time for an interrupt service
routine). AFAIR it worked like this:


*Initialization

ORCC #$50   *Disable IRQ, FIRQ
LDA  #$FF
TFR  A,DP
LDA  #$FE
ANDA $01
STA  $01    *Disable PIA-HS-IRQ
LDA  $03
ORA  #$03
STA  $03    *Enable PIA-FS-IRQ
LDD  #$FEFE
ANDA $21
STA  $21    *Disable PIA-CD-FIRQ
ANDB $23
STB  $23    *Disable PIA-CART-FIRQ

[...]

*Wait for the FS-Interrupt

SYNC
LDA  $02    *Clear Interrupt condition

[...]